1. Field of the Invention
This invention relates generally to a semiconductor large scale integrated circuit (LSI), and more particularly to a dynamic logic circuit which will be suitable for accomplishing a Bi-CMOS LSI for a high speed logic circuit.
2. Description of the Prior Art
The circuit disclosed in Japanese Patent Laid-Open No. 163716/1986 is known as a high speed dynamic logic circuit for an MOS LSI consisting of a logic portion for effecting predetermined logic calculations by a dynamic operation, which consists of MOS FETs, and a Bi-CMOS output buffer portion for outputting the result of calculation.
An example of the prior art technique described above is depicted in FIG. 6 of the accompanying drawings. In this example, a logic portion 25 consisting of a PMOS FET 30 and NMOS FETs 32-35 executes predetermined logic calculation for those signals which are inputted to data signal input terminals 42-44 and the result of calculation is outputted to a node 41. This output is inputted to an output buffer portion 26 consisting of a PMOS FET 31, NMOS FETs 36-38 and NPN bipolar transistors 39, 40 to produce an output from an output signal terminal 13.
Generally, the operation of a dynamic logic circuit consists of a precharge operation which is carried out in preparation before calculation and a calculation operation which continues the former. In the prior art example described above, these operations are carried out in the following way. First of all, a clock signal input terminal 7 is set to a ground potential to execute the pre-charge operation. As a result, the PMOS FET 30 is turned ON while NMOS FETs 35 and 38 are turned OFF. The potential of a node 41 rises to a power source potential and NMOS FETs 36 and 37 are turned ON while PMOS FET 31 are turned OFF. A bipolar transistor 39 is turned OFF. Furthermore, a base current flows through a bipolar transistor 40 through the MOS FET 37 to turn ON this transistor and a parasitic capacitance is discharged to reduce the potential. At this time, since an output signal terminal 13 is connected to a logic circuit of a next stage, the potential is preferably reduced down to the ground potential in order to secure a noise margin. In the circuit of the prior art technique described above, however, the bipolar transistor 40 is turned OFF when the potential of the output signal terminal drops to the base-emitter junction voltage V.sub.BE (approx. 0.7 V) of the bipolar transistor, and does not drop below this potential. Therefore, the drop of noise margin is likely to occur during the operation of LSI.
Next, in order to execute calculation, a terminal 7 is set to the power source potential. Accordingly, NMOS FETs 35 and 38 are turned 0N while PMOS FET 30 is turned OFF. If the node 41 and the ground are connected by data inputted to input terminals 42-44 in this instance, the potential of this node drops so that NMOS FETs 36 and 37 are turned OFF while PMOS FET 31 is turned ON, the potential of a node 46 rises, turning ON a bipolar transistor 39. Therefore, the parasitic capacitance 12 is charged and the output potential rises. Even if the potential of the node 41 starts dropping in this calculation operation, the potential of the node 46 does not rise until it is above the threshold voltage of a CMOS inverter consisting of MOS FETs 31 and 36. Accordingly, turn-ON of the bipolar transistor 39 is delayed and the delay time increases.
Furthermore, since this example uses as many as four MOSFETs and two bipolar transistors in the buffer portion, the layout area increases, thereby impeding higher integration of LSI.